Matrix decomposition in an integrated circuit device

ABSTRACT

Circuitry speeds up the Cholesky decomposition of a matrix. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry implements the following equation: 
               l   ij     =         a   ij     -     〈       L   i     ,     L   j       〉             a   jj     -     〈       L   j     ,     L   j       〉                 
When any l ij  term is calculated this way, the latency in calculating the l jj  term in the denominator has little or no effect on the l ij  term calculation. And if the calculations are properly pipelined, once the pipeline is filled, a new term can be output on each clock cycle or every few clock cycles.

BACKGROUND OF THE INVENTION

This invention relates to performing Cholesky decomposition operations in integrated circuit devices, and particularly in programmable integrated circuit devices such as programmable logic devices (PLDs).

Certain matrix operations require that a matrix be factored. For example, factoring a matrix may be necessary when a matrix is to be inverted. The result may be a “triangulated” matrix—i.e., a matrix with no values above the diagonal. The consequence is that only the values on the diagonal, and in the columns below those values, need to be calculated.

In Cholesky decomposition, to factor a matrix a, the first element l_(jj), at the top of each column in the resultant triangulated matrix l, may be calculated as: l _(jj) =√{square root over (a_(jj) −

L _(j) ,L _(j)

)} where a_(jj) is the jjth element of the original matrix a, and L_(j) is vector representing the jth row of matrix l up to the (j−1)th column. The subsequent elements in the jth column may be calculated as:

$l_{ij} = \frac{a_{ij} - \left\langle {L_{i},L_{j}} \right\rangle}{l_{jj}}$ where a_(ij) is the ijth element of the original matrix a, and L_(i) is vector representing the portion of the ith row of matrix l up to the (j−1)th column. To perform this calculation, the l_(jj) term needs to be calculated before any of the l_(ij) elements can be calculated. The inner product in each term—which, in the case of all real values is the same as a dot product, but in the case of complex values requires taking the complex conjugate of the second vector—may require dozens of clock cycles. Moreover, the square root calculation in the computation of l_(jj) can also take dozens of clock cycles.

SUMMARY OF THE INVENTION

The present invention relates to circuitry for speeding up the Cholesky decomposition of a matrix. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD).

The present invention is based on a recognition that if the first of the two equations above is substituted into the second equation, the result is the following:

$l_{ij} = \frac{a_{ij} - \left\langle {L_{i},L_{j}} \right\rangle}{\sqrt{a_{jj} - \left\langle {L_{j},L_{j}} \right\rangle}}$ When any l_(ij) term is calculated this way, the latency in calculating the l_(jj) term in the denominator has little or no effect on the l_(ij) term calculation, if the quantity that whose square root is being taken for the l_(jj) term is identical in structure to the numerator (although having different values). The denominator term (before the square root is taken) and all of the following numerator terms can be burst into the same datapath, while the denominator term is latched and used as the input to a second datapath. The second datapath multiplies the datapath output by the inverse square root of the latched value. And if the calculations are properly pipelined, once the pipeline is filled, a new term can be output on each clock cycle.

Therefore, in accordance with the present invention, there is provided matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below those resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of the resultant matrix corresponding to respective elements of the input matrix, and a subtractor for subtracting each respective inner product from the corresponding respective element of the input matrix to output respective inner product difference elements corresponding to the respective elements of the input matrix. The matrix decomposition circuitry also includes an inverse square root multiplication path including a first storage element for latching a particular one of the respective inner product difference elements, inverse square root circuitry that computes an inverse square root of that particular one of the respective inner product difference elements, and a multiplier that multiplies that inverse square root by an output of the inner product computation path. A pipeline stage between the inner product computation path and the inverse square root multiplication path is provided, whereby each of the respective inner product difference elements is multiplied by the inverse square root of that particular one of the respective inner product difference elements to output a respective one of resultant matrix elements.

A method of configuring such circuitry on a programmable device, a programmable device so configurable, and a machine-readable data storage medium encoded with software for performing the method, are also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 shows an example resultant matrix of a Cholesky decomposition operation;

FIG. 2 shows one embodiment, according to the invention, of a datapath arrangement for Cholesky decomposition;

FIG. 3 shows one embodiment, according to the invention, of a circuit arrangement used in the performance of Cholesky decomposition;

FIG. 4 is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention;

FIG. 5 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine executable instructions for performing the method according to the present invention; and

FIG. 6 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention.

DETAILED DESCRIPTION OF THE INVENTION

An example 100 of a triangulated matrix l resulting from a Cholesky decomposition is shown in FIG. 1. Although the size of matrix l may differ, matrix l will always be a square matrix. In this case, matrix l is a 6-by-6 matrix. The elements on the diagonal are l₁₁, . . . , l₆₆. In each jth column, the elements under l_(jj) are l_(ij), i=j+1, . . . , i_(max) (in this case, i_(max)=6). The matrix may be considered to be empty above the diagonal, or the elements above the diagonal may be considered to be zeroes.

Each element l_(ij) can be calculated using two datapaths. The first datapath calculates the following result: l _(x) =a _(x) −

L _(x) ,L _(x)

where for l and a, x=ij; for the L vectors, x=i or j, respectively; and

L_(x),L_(x)

denotes the inner product of the L vectors.

The first output (x=jj) of the first datapath is latched at the input of a second datapath, which calculates the actual l_(ij). The first element of the column (l_(jj)) is calculated as the inverse square root of the input (a_(jj)−

L_(j),L_(j)

), multiplied by the input, generating the square root of the input. The inverse square root is used instead of a direct square root calculation, because it can be reused for the following elements in the column using multiplication, which is easier to implement than division.

To calculate all of the subsequent values in the column, the latched first datapath output is used for the inverse square root input which is a first multiplier input, and the other multiplier input is, for each subsequent term, the corresponding output of the first datapath. The entire column can therefore be calculated without waiting for any individual element to be finished.

FIG. 2 shows how the matrix values can be stored for fast access. Each a_(ij) value is a single number that can be addressed in a single clock cycle, but each L_(i) or L_(j) row vector is j−1 numbers which would require j−1 clock cycles to address if all values were stored in a single memory. However, in accordance with an embodiment of the present invention, matrix a may be stored in a single memory 201, while each column of matrix l may be stored in one of a plurality of i_(max) separate memories 202. The ith element of each of the separate column memories can be addressed simultaneously, allowing the entire row vector to be read out within a single clock cycle. This may be referred to as a “column-wise” memory architecture.

For example, programmable logic devices available from Altera Corporation, of San Jose, Calif., may have a smaller number of larger memory blocks (e.g., 144 kb memory blocks), one of which could be used as memory 201 to store matrix a, and a larger number of smaller memory blocks (e.g., 9 kb memory blocks), i_(max) of which could be used as memories 202 to separately store the columns of matrix l. Of course, it is not necessary to use different sizes of memories for memories 201, 202; if a sufficient number of larger memories is available, any one or more of the memories used as column memories 202 to separately store the columns of matrix l may be the same size as (or even larger than) the memory used as memory 201 to store matrix a.

Thus, in a single clock cycle, address input 211 may be applied to memory 201 to read out matrix element a_(ij) at 221 for input to calculation datapath 300, while address input 212 may be applied to the appropriate j−1 memories 202 on path 203 to read out vector L_(i), and address input 222 may be applied to the appropriate j−1 memories 202 on path 213 to read out vector L_(j). The outputs 221, 203, 213 may be input to calculation datapath 300, described in more detail in connection with FIG. 3, which outputs the individual l_(ij) values at 204, and also feeds each back at 205 into the respective jth column memory 202.

Datapath 300, which may be implemented in fixed or programmable logic, includes inner product datapath 301 and inverse square root datapath 302.

Inner product datapath 301 includes inner product generator 311 and subtractor 321 to subtract the inner product from a_(ij). Inner product generator 311 may include a sufficient plurality of multipliers and adders to simultaneously multiply i_(max) pairs of values, and then add those products together. For complex vectors, inner product generator 311 may include sufficient multipliers and adders to simultaneously multiply 2(i_(max)) pairs of values, and also may include the necessary components to compute the complex conjugate values for L_(j) in the case where the values are complex. The L_(j) term is latched in register 331 at the beginning of a column process and is not changed until the next column is started.

Starting with the second column, the first output of inner product datapath 301 for each column—i.e., each l_(jj)—is latched into register 312 as the input to inverse square root datapath 302 for the duration of calculation of that column. Inverse square root datapath 302 includes inverse square root module 322 for calculating the inverse square root of l_(jj), and multiplier 332 for multiplying the inverse square root by the current l_(ij). The latching of l_(jj) into register 312 delays its input to multiplier 332 by one clock cycle. Therefore, the input of l_(ij) to multiplier 332 also is delayed, by register 342, so that latency is the same for both inputs.

For the first column, terms are generated using simple division. The top term, l₁₁ is a₁₁ ^(−0.5) and all the subsequent inputs for the first column are also divided by a₁₁—i.e., l_(i1)=a_(i1)/a₁₁ ^(−0.5). This is accomplished using multiplexer 350 to allow the a_(ij) inputs 351 to bypass inner product datapath 301.

In addition to increasing the number of multipliers and adders in inner product generator 311, as discussed above, some other relatively minor additions (not shown) would be made to datapath 300 where the inputs are complex. In such a case, the L_(i), L_(j) vector values will be complex. This will require generating the complex conjugate of the vector value latched in register 331. That can be done by providing logic to invert the sign bit of the imaginary portion of each value. The changes required in inverse square root datapath 302 are simplified by the nature of matrix l. The diagonal values—i.e., the first value at the top of each column in the Cholesky decomposition—is always real, meaning that inverse square root calculation 322 will always be real. Therefore, while the other multiplicand at multiplier 332 is complex, the multiplication will be one of a complex value by a real scalar value, so only two multipliers—i.e., one additional multiplier—are required.

Thus it is seen that, for each column, once the first resultant element l_(jj) has been calculated and latched, the subsequent inner products can be generated one per clock and pipelined for calculation of subsequent resultant elements l_(ij). Once the pipeline is full, those subsequent resultant elements l_(ij) can then be output once per clock.

The various operators used for the calculations described above can be configured in a programmable device using, e.g., the techniques described in copending, commonly-assigned U.S. patent application Ser. No. 11/625,655, filed Jan. 22, 2007, which is hereby incorporated by reference herein in its entirety.

One potential use for the present invention may be in programmable integrated circuit devices such as programmable logic devices, where programming software can be provided to allow users to configure a programmable device to perform matrix operations. The result would be that fewer logic resources of the programmable device would be consumed. And where the programmable device is provided with a certain number of dedicated blocks for arithmetic functions (to spare the user from having to configure arithmetic functions from general-purpose logic), the number of dedicated blocks needed to be provided (which may be provided at the expense of additional general-purpose logic) can be reduced (or sufficient dedicated blocks for more operations, without further reducing the amount of general-purpose logic, can be provided).

Instructions for carrying out a method according to this invention for programming a programmable device to perform matrix decomposition may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming or configuring PLDs or other programmable devices to perform addition and subtraction operations as described above. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif.

FIG. 4 presents a cross section of a magnetic data storage medium 800 which can be encoded with a machine executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 800 can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate 801, which may be conventional, and a suitable coating 802, which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium 800 may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device.

The magnetic domains of coating 802 of medium 800 are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, in accordance with the invention.

FIG. 5 shows a cross section of an optically-readable data storage medium 810 which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium 810 can be a conventional compact disk read-only memory (CD-ROM) or digital video disk read-only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium 810 preferably has a suitable substrate 811, which may be conventional, and a suitable coating 812, which may be conventional, usually on one or both sides of substrate 811.

In the case of a CD-based or DVD-based medium, as is well known, coating 812 is reflective and is impressed with a plurality of pits 813, arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating 812. A protective coating 814, which preferably is substantially transparent, is provided on top of coating 812.

In the case of magneto-optical disk, as is well known, coating 812 has no pits 813, but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating 812. The arrangement of the domains encodes the program as described above.

A PLD 90 programmed according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system 900 shown in FIG. 6. Data processing system 900 may include one or more of the following components: a processor 901; memory 902; I/O circuitry 903; and peripheral devices 904. These components are coupled together by a system bus 905 and are populated on a circuit board 906 which is contained in an end-user system 907.

System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 90 can be used to perform a variety of different logic functions. For example, PLD 90 can be configured as a processor or controller that works in cooperation with processor 901. PLD 90 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 90 can be configured as an interface between processor 901 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.

Various technologies can be used to implement PLDs 90 as described above and incorporating this invention.

It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow. 

1. Matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below said resultant matrix elements on said diagonal, and having no nonzero matrix elements in said columns above said resultant matrix elements on said diagonal, said matrix decomposition circuitry comprising: an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of said resultant matrix corresponding to respective elements of said input matrix, and a subtractor for subtracting each said respective inner product from said respective element of said input matrix to output respective inner product difference elements corresponding to said respective elements of said input matrix; an inverse square root multiplication path including a first storage element for latching a particular one of said respective inner product difference elements, inverse square root circuitry that computes an inverse square root of said particular one of said respective inner product difference elements, and a multiplier that multiplies said inverse square root by an output of said inner product computation path; and a pipeline stage between said inner product computation path and said inverse square root multiplication path; whereby: each of said respective inner product difference elements is multiplied by said inverse square root of said particular one of said respective inner product difference elements to output a respective one of resultant matrix elements.
 2. The matrix decomposition circuitry of claim 1 wherein: said inner product computation path further comprises a second storage element for latching a particular one of said row vectors; whereby: said respective inner products are calculated from said particular one of said row vectors and each respective one of said row vectors.
 3. The matrix decomposition circuitry of claim 2 wherein said particular one of said respective inner product difference elements and said particular one of said row vectors correspond to one of said resultant matrix elements on said diagonal.
 4. A method of configuring a programmable integrated circuit device as matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below said resultant matrix elements on said diagonal, and having no nonzero matrix elements in said columns above said resultant matrix elements on said diagonal, said method comprising: configuring logic of said programmable integrated circuit device as an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of said resultant matrix corresponding to respective elements of said input matrix, and a subtractor for subtracting each said respective inner product from said respective element of said input matrix to output respective inner product difference elements corresponding to said respective elements of said input matrix; configuring logic of said programmable integrated circuit device as an inverse square root multiplication path including a first storage element for latching a particular one of said respective inner product difference elements, inverse square root circuitry that computes an inverse square root of said particular one of said respective inner product difference elements, and a multiplier that multiplies said inverse square root by an output of said inner product computation path; and configuring logic of said programmable integrated circuit device as a pipeline stage between said inner product computation path and said inverse square root multiplication path; whereby: said configured logic multiplies each of said respective inner product difference elements by said inverse square root of said particular one of said respective inner product difference elements to output a respective one of resultant matrix elements.
 5. The method of claim 4 further comprising configuring logic of said programmable integrated circuit device as a second storage element in said inner product computation path, for latching a particular one of said row vectors; whereby: said configured logic calculates said respective inner products from said particular one of said row vectors and each respective one of said row vectors.
 6. The method of claim 5 wherein said particular one of said respective inner product difference elements and said particular one of said row vectors correspond to one of said resultant matrix elements on said diagonal.
 7. A programmable integrated circuit device comprising: logic configurable as an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of said resultant matrix corresponding to respective elements of said input matrix, and a subtractor for subtracting each said respective inner product from said respective element of said input matrix to output respective inner product difference elements corresponding to said respective elements of said input matrix; logic configurable as an inverse square root multiplication path including a first storage element for latching a particular one of said respective inner product difference elements, inverse square root circuitry that computes an inverse square root of said particular one of said respective inner product difference elements, and a multiplier that multiplies said inverse square root by an output of said inner product computation path; and logic configurable as a pipeline stage between said inner product computation path and said inverse square root multiplication path; whereby: said logic is configurable to multiply each of said respective inner product difference elements by said inverse square root of said particular one of said respective inner product difference elements to output a respective one of resultant matrix elements.
 8. The programmable integrated circuit device of claim 7 further comprising logic configurable as a second storage element in said inner product computation path, for latching a particular one of said row vectors; whereby: said logic is configurable to calculate said respective inner products from said particular one of said row vectors and each respective one of said row vectors.
 9. The programmable integrated circuit device of claim 8 wherein said particular one of said respective inner product difference elements and said particular one of said row vectors correspond to one of said resultant matrix elements on said diagonal.
 10. A machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device as matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below said resultant matrix elements on said diagonal, and having no nonzero matrix elements in said columns above said resultant matrix elements on said diagonal, said instructions comprising: instructions to configure logic of said programmable integrated circuit device as an inner product computation path including a plurality of multipliers and adders for computing respective inner products of row vectors of said resultant matrix corresponding to respective elements of said input matrix, and a subtractor for subtracting each said respective inner product from said respective element of said input matrix to output respective inner product difference elements corresponding to said respective elements of said input matrix; instructions to configure logic of said programmable integrated circuit device as an inverse square root multiplication path including a first storage element for latching a particular one of said respective inner product difference elements, inverse square root circuitry that computes an inverse square root of said particular one of said respective inner product difference elements, and a multiplier that multiplies said inverse square root by an output of said inner product computation path; and instructions to configure logic of said programmable integrated circuit device as a pipeline stage between said inner product computation path and said inverse square root multiplication path; whereby: said instructions cause logic to be configured to multiply each of said respective inner product difference elements by said inverse square root of said particular one of said respective inner product difference elements to output a respective one of resultant matrix elements.
 11. The machine-readable data storage medium of claim 10 wherein said instructions further comprise: instructions to configure logic of said programmable integrated circuit device as a second storage element in said inner product computation path, for latching a particular one of said row vectors; whereby: said instructions cause logic to be configured to calculate said respective inner products from said particular one of said row vectors and each respective one of said row vectors.
 12. The machine-readable data storage medium of claim 11 wherein said particular one of said respective inner product difference elements and said particular one of said row vectors correspond to one of said resultant matrix elements on said diagonal. 